Random access memory (RAM) devices, such as dynamic RAMs (DRAMs), typically include a memory array of DRAM cells accessed via wordlines (e.g., in a row direction) and bit lines (e.g., in column direction). A typical DRAM cell includes a pass transistor and a storage capacitor. In a read operation, the pass transistor (e.g., transfer device) is turned on according the voltage of a wordline to enable the transfer (i.e., sharing) of charge on a corresponding bit line. For high performance and/or compact array design, a pass transistor is typically an n-channel insulated gate field effect transistor (i.e., NFET).
For efficient DRAM operation, a word line voltage is often driven to a “boosted” voltage. A boosted voltage can be a level higher than a supply voltage to the DRAM device or DRAM array. A boosted voltage can ensure that there is virtually no threshold drop introduced by a pass transistor as charge is transferred from a selected DRAM cell to a bit line.
In smaller dimension technologies, to decrease access time, a threshold voltage (Vt) of the transfer device within a memory cell can be reduced and/or the thickness of the transfer gate dielectric can be reduced. This can allow for lower boosted wordline voltages. However, such an arrangement can increase a sub-threshold leakage of a transfer device. A sub-threshold leakage can be the leakage that occurs even though the transfer device is (or is meant to be) turned off. Increased sub-threshold leakage can deplete charge from the storage capacitor of a DRAM cell and hence negatively impacts data retention time.
To address increased sub-threshold leakage, a transfer device off voltage can be increased. For example, in the case of an NFET, a low wordline voltage can be driven to a voltage below a low power supply (e.g., ground) level.
Therefore, in order to provide efficient data transfer and faster access times, a wordline driver circuit can drive a corresponding wordline to a boosted positive voltage (Vpp) to access a memory cell and boosted negative voltage (Vnwl) to isolate a memory cell.
Generally, providing boosted voltage levels can entail an equivalent charge reservoir for both a Vpp level and Vnwl level in order to supply the instantaneous charge source or sink needed to activate (e.g., drive to Vpp) and de-activate (e.g., drive to Vnwl) the wordline.
To better understand various aspects of the disclosed embodiments, a conventional DRAM wordline driver will be described with reference to FIG. 9.
Referring to FIG. 9, a conventional wordline driver circuit 900 can include a dynamic high voltage NAND decoder 902 connected to a keeper half-latch 904. It is noted that these two circuit sections (902 and 904) operate a boosted high voltage Vpp. These circuit sections can be followed by boosted level inverters 906 and 908. Boosted inverters (906 and 908) can operate between the boosted levels, driving output signals between a boosted high voltage Vpp and a boosted low voltage Vnwl.
A final stage of wordline driver 900 can include a decoded driver 910. Decoded driver 910 can include a p-channel insulated gate field effect transistor (i.e., PFET) P1 with a source driven by a decoded boosted high voltage DRV_Vpp, and an NFET N1 having a source coupled to the boosted low voltage Vnwl. In addition, a keeper NFET N2 can dynamically maintain the wordline (WL) at the boosted low voltage Vnwl, when not selected via the source of P1.
While the conventional arrangement of FIG. 9 represents an improvement over previous architectures that did not provide a wordline voltage driven to a boosted low voltage, the arrangement can have a number of drawbacks or disadvantages. First, a wordline driver 900 includes a dynamic NAND precharge PFET P2 that drives a decoder node ND1 to a boosted high voltage Vpp. As a result, when multiple wordline drivers are cycled to a precharge state (signal PRECH low), multiple nodes ND1 are driven to boosted high voltage Vpp, which can cause a large current spike on a Vpp supply.
Further, as a wordline is discharged to a boosted low (Vnwl) level, a significant current spike for such a supply can be created. This can cause a Vnwl supply to “bounce” (rise above its intended level). This can cause sub-threshold leakage in transfer devices that should otherwise be maintained in the fully off state.
Still further, in order to accommodate large voltage spikes at both boosted levels, a DRAM device may have to be supplied with a relatively large decoupling capacitor to both a boosted high voltage Vpp, as well as a boosted low voltage Vnwl.
Accordingly, there is a need for a wordline driver that can drive a wordline between boosted high and low voltages that can reduce active current spikes on boosted supplies.
More particularly, it would be desirable to arrive at some way of reducing a current spike on a boosted high supply (e.g., Vpp) when dynamic decoders of wordline drivers are commonly activated in response to a precharge operation.
It would also be desirable to arrive at some way of reducing a bounce in a boosted low supply resulting from current spikes caused by discharging wordlines to such a boosted low supply voltage.
It is also desirable to arrive at a wordline driver that can essentially eliminate the need for relatively large decoupling capacitors for a boosted low voltage and boosted high voltage.